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LTC3717-1 Wide Operating Range, No RSENSETM Step-Down Controller for DDR/QDR Memory Termination
FEATURES
s s
DESCRIPTIO
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s s s s s s s s s s s s
VOUT = 1/2 VREF Adjustable and Symmetrical Sink/Source Current Limit up to 20A True Current Mode Control with Optional Use of Sense Resistor VON and ION Pins Allow Constant Frequency Operation During Input and Output Voltage Changes 0.65% Output Voltage Accuracy Up to 97% Efficiency Ultrafast Transient Response 2% to 90% Duty Cycle at 200kHz tON(MIN) 100ns Stable with Ceramic COUT Power Good Output Voltage Monitor Wide VIN Range: 4V to 36V Adjustable Switching Frequency up to 1.5MHz Output Overvoltage Protection Optional Short-Circuit Shutdown Timer Available in a 5mm x 5mm QFN Package
The LTC(R)3717-1 is a synchronous step-down switching regulator controller for double data rate (DDR) and Quad Data RateTM (QDRTM) memory termination. The controller uses a valley current control architecture to deliver very low duty cycles with or without a sense resistor. Operating frequency is selected by an external resistor and is compensated for variations in VIN and VOUT. Forced continuous operation reduces noise and RF interference. Output voltage is internally set to half of VREF, which is user programmable. Fault protection is provided by an output overvoltage comparator and optional short-circuit shutdown timer. Soft-start capability for supply sequencing is accomplished using an external timing capacitor. The regulator current limit level is symmetrical and user programmable. Wide supply range allows operation from 4V to 36V at the VCC input.
, LTC and LT are registered trademarks of Linear Technology Corporation. No RSENSE is a trademark of Linear Technology Corporation. QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, Hitachi, IDT, Micron Technology, Inc. and Samsung.
APPLICATIO S
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Bus Termination: DDR and QDR Memory, SSTL, HSTL, ... Notebook Computers, Desktop Servers Tracking/Margining Power Supply
TYPICAL APPLICATIO
VCC 5V TO 28V 1F 0.1F VCC ION VREF RUN/SS TG LTC3717-1 SW SENSE + ITH BOOST SGND VON PGOOD DRVCC INTVCC BG
715k VDD = 2.5V Si7840DP B320A
+
VIN 2.5V TO 5.5V 150F 6.3V x2
EFFICIENCY (%)
100 90 80 70 60 50 40 30 20 10 VIN = 5V VIN = 2.5V
470pF
20k
0.22F CMDSH-3 Si7840DP 4.7F
0.68H
+
VOUT 1.25V 180F 10A 4V x2
+
B320A
PGND SENSE - VFB
37171 F01a
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Figure 1. High Efficiency DDR Memory Termination Supply
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Efficiency vs Load Current
VOUT = 1.25V 0 2 4 6 8 10 LOAD CURRENT (A) 12 14
37171 F01b
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LTC3717-1
ABSOLUTE
(Note 1)
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RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW
Boosted Topside Driver Supply Voltage (BOOST) ............................................... 42V to - 0.3V VIN, ION, SW, SENSE+ Voltage .................. 36V to - 0.3V EXTVCC, DRVCC, RUN/SS, PGOOD, (BOOST - SW) Voltages ............................ 7V to - 0.3V VON, VREF, VRNG Voltages .......(INTVCC + 0.3V) to - 0.3V ITH, VFB Voltages...................................... 2.7V to - 0.3V TG, BG, INTVCC, EXTVCC, DRVCC Peak Currents ....... 2A TG, BG, INTVCC, EXTVCC, DRVCC RMS Currents .. 50mA Operating Ambient Temperature Range (Note 4) ................................... - 40C to 85C Junction Temperature (Note 2) ............................ 125C Storage Temperature Range ................. - 65C to 125C Reflow Peak Body Temperature ............................ 260C
RUN/SS
BOOST
NC
NC
NC
NC
32 31 30 29 28 27 26 25 VON 1 PGOOD 2 VRNG 3 ITH 4 SGND 5 ION 6 VFB 7 NC 8 9 10 11 12 13 14 15 16 33 24 SW 23 SENSE+ 22 NC 21 SENSE- 20 PGND 19 BG 18 DRVCC 17 INTVCC
NC
UH PACKAGE 32-LEAD (5mm x 5mm) PLASTIC QFN
TJMAX = 125C, JA = 34C/ W EXPOSED PAD IS SGND (PIN 33) MUST BE SOLDERED TO PCB
ORDER PART NUMBER LTC3717EUH-1
QFN PART MARKING 37171
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
SYMBOL Buck Regulator IQ(VIN) Input DC Supply Current (VIN) Normal Shutdown Supply Current Feedback Voltage Accuracy Feedback Voltage Line Regulation Feedback Voltage Load Regulation Error Amplifier Transconductance On-Time Minimum On-Time Minimum Off-Time Maximum Current Sense Threshold VPGND - VSW (Source) Minimum Current Sense Threshold VPGND - VSW (Sink) PARAMETER
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25C. VIN = 15V, unless otherwise noted.
CONDITIONS MIN TYP MAX UNITS
EXTVCC
VREF
VIN
NC
NC
NC
NC
NC
TG
VRUN/SS = 0V ITH = 1.2V (Note 3), VREF = 2.4V VIN = 4V to 36V, ITH = 1.2V (Note 3) ITH = 0.5V to 1.9V (Note 3) ITH = 1.2V (Note 3) ION = 30A, VON = 0V ION = 60A, VON = 0V ION = 180A VRNG = 1V, VFB = VREF/2 - 50mV VRNG = 0V, VFB = VREF/2 - 50mV VRNG = INTVCC, VFB = VREF/2 - 50mV VRNG = 1V, VFB = VREF/2 + 50mV VRNG = 0V, VFB = VREF/2 + 50mV VRNG = INTVCC, VFB = VREF/2 + 50mV
q q q q q q q q
1000 15 - 0.65 0.1 0.002 - 0.05 0.93 186 95 1.13 233 115 50 300 108 76 148 -140 -97 - 200 135 95 185 -165 -115 - 235
2000 30 0.65 - 0.3 1.33 280 135 100 400 162 114 222 -190 -133 - 270
VFB VFB(LINE) VFB(LOAD) gm(EA) tON tON(MIN) tOFF(MIN) VSENSE(MAX)
VSENSE(MIN)
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A A % %/V % mS ns ns ns ns mV mV mV mV mV mV
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LTC3717-1
ELECTRICAL CHARACTERISTICS
SYMBOL VFB(OV) VFB(UV) VRUN/SS(ON) VRUN/SS(LE) VRUN/SS(LT) IRUN/SS(C) IRUN/SS(D) VIN(UVLO) TG RUP TG RDOWN BG RUP BG RDOWN TG tr TG tf BG tr BG tf VINTVCC VEXTVCC VEXTVCC VEXTVCC(HYS) PGOOD Output VFBH VFBL VFB(HYS) VPGL PGOOD Upper Threshold PGOOD Lower Threshold PGOOD Hysteresis PGOOD Low Voltage PARAMETER Output Overvoltage Fault Threshold Output Undervoltage Threshold RUN Pin Start Threshold RUN Pin Latchoff Enable RUN Pin Latchoff Threshold Soft-Start Charge Current Soft-Start Discharge Current VIN Undervoltage Lockout TG Driver Pull-Up On Resistance TG Driver Pull-Down On Resistance BG Driver Pull-Up On Resistance BG Driver Pull-Down On Resistance TG Rise Time TG Fall Time BG Rise Time BG Fall Time Internal VCC Voltage EXTVCC Switchover Voltage EXTVCC Switch Drop Voltage EXTVCC Switchover Hysteresis
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25C. VIN = 15V, unless otherwise noted.
CONDITIONS MIN 8
q
TYP 10 - 25 1.5 4 3.5
MAX 12 2 4.5 4.2 -3 3 3.9 4.0
UNITS % % V V V A A V V ns ns ns ns
0.8
RUN/SS Pin Rising RUN/SS Pin Falling VRUN/SS = 0V VRUN/SS = 4.5V, VFB = 0V VIN Falling VIN Rising TG High (Note 5) TG Low (Note 5) BG High (Note 5) BG Low (Note 5) CLOAD = 3300pF CLOAD = 3300pF CLOAD = 3300pF CLOAD = 3300pF 6V < VCC < 30V, VEXTVCC = 4V ICC = 0mA to 20mA, VEXTVCC = 4V ICC = 20mA, VEXTVCC Rising ICC = 20mA, VEXTVCC = 5V
q q q q
- 0.5 0.8
-1.2 1.8 3.4 3.5 2 2 3 1 20 20 20 20
Internal VCC Regulator 4.7 4.5 5 - 0.1 4.7 150 200 VFB Rising (0% = 1/3 VREF) VFB Falling (0% = 1/3 VREF) VFB Returning (0% = 1/3 VREF) IPGOOD = 5mA 8 -8 10 - 10 1 0.15 12 - 12 2 0.4 300 5.3 2 V % V mV mV % % % V VLDO(LOADREG) Internal VCC Load Regulation
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: TJ is calculated from the ambient temperature TA and power dissipation PD as follows: LTC3717EUH-1: TJ = TA + (PD * 34C/W) Note 3: The LTC3717EUH-1 is tested in a feedback loop that adjusts VFB to achieve a specified error amplifier output voltage (ITH).
Note 4: The LTC3717EUH-1 is guaranteed to meet performance specifications from 0C to 70C. Specifications over the -40C to 85C operating temperature range are assured by design, characterization and correlation with statistical process controls. Note 5: RDS(ON) limit guaranteed by design and/or correlation to static test.
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LTC3717-1 TYPICAL PERFOR A CE CHARACTERISTICS
Efficiency vs Load Current
100 90 80 FREQUENCY (kHz) 70
EFFICIENCY (%)
VIN = 2.5V VOUT = 1.25V
60 50 40 30 20 10 0 0.01 0.1
VOUT/VIN (%)
FIGURE 1 CIRCUIT 1 10 LOAD CURRENT (A) 100
37171 G01
Load-Step Transient
VOUT 200mV/DIV
IL 5A/DIV
VIN = 2.5V 20s/DIV VOUT = 1.25V LOAD = 500mA TO 10A STEP FIGURE 1 CIRCUIT
Load Regulation
0 -0.1 VIN = 2.5V VOUT = 1.25V
1000
VOUT/VOUT (%)
ON-TIME (ns)
600
-0.3 -0.4 -0.5 FIGURE 1 CIRCUIT -0.6 0 1 2 34567 LOAD CURRENT (A) 8 9 10
ON-TIME (ns)
-0.2
4
UW
37171 G04
VOUT/VIN Tracking Ratio vs Input Voltage
50.00 49.95 49.90 LOAD = 1A 49.85 LOAD = 10A 49.80 49.75 49.70 FIGURE 1 CIRCUIT 49.65 1.5 1.7 1.9 2.1 2.3 2.5 INPUT VOLTAGE (V) 2.7 2.9
37171 G02
Frequency vs Input Voltage
450 400 350 300 250 200 150 100 50 0 1.5 1.7 1.9 2.1 2.3 2.5 INPUT VOLTAGE (V) 2.7 2.9
37171 G03
LOAD = 0A
LOAD = 10A
LOAD = 0A
VOUT = 1.25V FIGURE 1 CIRCUIT
Start-Up Response
VOUT 1V/DIV
IL 2A/DIV
37171 G05
VIN = 2.5V 4ms/DIV VOUT = 1.25V LOAD = 0.2 FIGURE 1 CIRCUIT
37171 G06
On-Time vs VON Voltage
IION = 30A 300 250 200 150 100 200 50
On-Time vs Temperature
IION = 30A
800
400
0
0
2 1 VON VOLTAGE (V)
3
37171 G07
0 -50 -25
50 25 75 0 TEMPERATURE (C)
100
125
37171 G08
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LTC3717-1 TYPICAL PERFOR A CE CHARACTERISTICS
On-Time vs ION Current
10k VVON = 0V 0
FCB PIN CURRENT (A)
ON-TIME (ns)
1k
INTVCC (%)
100
10 1 10 ION CURRENT (A) 100
37171 G09
RUN/SS Latchoff Thresholds vs Temperature
UNDERVOLTAGE LOCKOUT THRESHOLD (V)
5.0
4.0
MAXIMUM CURRENT SENSE THRESHOLD (mV)
RUN/SS THRESHOLD (V)
4.5 LATCHOFF ENABLE 4.0
3.5 LATCHOFF THRESHOLD
3.0 -50
-25
75 0 25 50 TEMPERATURE (C)
Maximum Current Sense Threshold vs RUN/SS Voltage, VRNG = 1V
MAXIMUM CURRENT SENSE THRESHOLD (mV)
MAXIMUM CURRENT SENSE THRESHOLD (mV)
160 140 120 100 80 60 40 20 0 2.0 2.2 2.4 2.6 2.8 3.0 RUN/SS (V) 3.2 3.4 3.6
37171 G15
100 80 60 40 20 0 -50 -30 -10 10 30 50 70 90 110 130 TEMPERATURE (C)
37171 G16
gm (mS)
UW
100
37171 G12
INTVCC Load Regulation
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RUN/SS Latchoff Thresholds vs Temperature
-0.1
2 PULL-DOWN CURRENT 1
-0.2
-0.3
0 PULL-UP CURRENT -1
-0.4
-0.5
0
10 30 40 20 INTVCC LOAD CURRENT (mA)
50
37171 G10
-2 -50 -25
50 25 0 75 TEMPERATURE (C)
100
125
37171 G11
Undervoltage Lockout Threshold vs Temperature
300 250 200 150 100 50
Maximum Current Sense Threshold vs VRNG Voltage
3.5
3.0
2.5
125
2.0 -50 -25
75 0 25 50 TEMPERATURE (C)
100
125
0 0.50
0.75
1.00
1.25 1.50 VRNG (V)
1.75
2.00
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Maximum Current Sense Threshold vs Temperature, VRNG = 1V
180 160 140 120 1.50 1.40 1.30 1.20 1.10 1.00 0.90 0.80
Error Amplifier gm vs Temperature
0.70 -50 -30 -10 10 30 50 70 90 110 130 TEMPERATURE (C)
37171 G17
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LTC3717-1
PI FU CTIO S
VON (Pin 1): On-Time Voltage Input. Voltage trip point for the on-time comparator. Tying this pin to the output voltage makes the on-time proportional to VOUT. The comparator input defaults to 0.7V when the pin is grounded, 2.4V when the pin is tied to INTVCC. PGOOD (Pin 2): Power Good Output. Open-drain logic output that is pulled to ground when the output voltage is not within 10% of the regulation point. VRNG (Pin 3): Sense Voltage Range Input. The voltage at this pin is ten times the nominal sense voltage at maximum output current and can be set from 0.5V to 2V by a resistive divider from INTVCC. The nominal sense voltage defaults to 70mV when this pin is tied to ground, 140mV when tied to INTVCC. ITH (Pin 4): Current Control Threshold and Error Amplifier Compensation Point. The current comparator threshold increases with this control voltage. The voltage ranges from 0V to 2.4V with 0.8V corresponding to zero sense voltage (zero current). SGND (Pin 5)/Exposed Pad (Pin 33): Signal Ground. All small-signal components and compensation components should connect to this ground, which in turn connects to PGND at one point. Pin 5 is electrically connected to the exposed pad. Exposed pad must be soldered to PCB. ION (Pin 6): On-Time Current Input. Tie a resistor from VIN to this pin to set the one-shot timer current and thereby set the switching frequency. VFB (Pin 7): Error Amplifier Feedback Input. This pin connects to VOUT and divides its voltage to 2/3 * VFB through precision internal resistors before it is applied to the input of the error amplifier. Do not apply more than 1.5V on VFB. For higher output voltages, attach an external resistor R2 (1/2 * R1 at VREF) from VOUT to VFB. NC (Pins 8, 9, 11, 12, 13, 14, 22, 25, 26, 29, 30, 32): Do Not Connect. VREF (Pin 10): Positive Input of Internal Error Amplifier. This pin connects to an external reference and divides its voltage to 1/3 VREF through precision internal resisters before it is applied to the positive input of the error amplifier. Reference voltage for output voltage, power good threshold, and short-circuit shutdown threshold. Do not apply more than 3V on VREF. If higher voltages are used, connect an external resistor (R1 160k) from voltage reference to VREF. EXTVCC (Pin 15): External VCC Input. When EXTVCC exceeds 4.7V, an internal switch connects this pin to INTVCC and shuts down the internal regulator so that controller and gate drive power is drawn from EXTVCC. Do not exceed 7V at this pin and ensure that EXTVCC < VIN. VIN (Pin 16): Main Input Supply. Decouple this pin to PGND with an RC filter (1, 0.1F). INTVCC (Pin 17): Internal Regulator Output. The control circuits are powered from this voltage when VIN is greater than 5V. Decouple this pin to power ground with a minimum of 4.7F low ESR tantalum or ceramic capacitor. DRVCC (Pin 18): Voltage Supply to Bottom Gate Driver. Normally connected to the INTVCC pin through a decoupling RC filter (1/0.1F). Decouple this pin to power ground with a minimum of 4.7F low ESR tantalum or ceramic capacitor. Do not exceed 7V at this pin. BG (Pin 19): Bottom Gate Drive. Drives the gate of the bottom N-channel MOSFET between ground and DRVCC. PGND (Pin 20): Power Ground. Connect these pins closely to the source of the bottom N-channel MOSFET, the (-) terminal of CVCC and the (-) terminal of CIN. SENSE - (Pin 21): Negative Current Sense Comparator Input. The (-) input to the current comparator is normally connected to power ground unless using a resistive divider from INTVCC (see Applications Information). SENSE + (Pin 23): Positive Current Sense Comparator Input. The (+) input to the current comparator is normally connected to the SW node unless using a sense resistor (see Applications Information). SW (Pin 24): Switch Node. The (-) terminal of the bootstrap capacitor CB connects here. This pin swings from a diode voltage drop below ground up to VIN. TG (Pin 27): Top Gate Drive. Drives the top N-channel MOSFET with a voltage swing equal to INTVCC superimposed on the switch node voltage SW.
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LTC3717-1
PI FU CTIO S
BOOST (Pin 28): Boosted Floating Driver Supply. The (+) terminal of the bootstrap capacitor CB connects here. This pin swings from a diode voltage drop below INTVCC up to VIN + INTVCC. RUN/SS (Pin 31): Run Control and Soft-Start Input. A capacitor to ground at this pin sets the ramp time to full output current (approximately 3s/F) and the time delay for overcurrent latchoff (see Applications Information). Forcing this pin below 0.8V shuts down the device.
FU CTIO AL DIAGRA
RON VON 1 6 ION
0.7V
2.4V
tON =
VVON (10pF) IION
+
ICMP
20k
-
1.4V OV VRNG 3
x
0.7V 5.7A
1 240k Q2 ITHB UV
Q1 Q5 OV
EA
VREF 10
R2 80k R1 40k
0.6V 4 ITH CC1
RC
+
-
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-
+
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15 EXTVCC 4.7V
16 VIN
+
CIN
VIN
+
-
0.8V REF 5V REG
BOOST 28 TG R S Q ON 27 SW 24 SENSE+ 23 IREV SWITCH LOGIC INTVCC 17 CVCC DRVCC SHDN 18 BG 19 PGND 20 SENSE - 21 PGOOD 2 M2 DB L1 VOUT CB M1
+ -
+
COUT
+ -
3/10VREF
R3 20k R4 40k
VFB 7
+ -
SS RUN SHDN 1.2A 11/30VREF
SGND 5
+ -
6V
37171 FD01
0.6V
31 RUN/SS CSS
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LTC3717-1
OPERATIO
Main Control Loop The LTC3717-1 is a current mode controller for DC/DC step-down converters. In normal operation, the top MOSFET is turned on for a fixed interval determined by a one-shot timer OST. When the top MOSFET is turned off, the bottom MOSFET is turned on until the current comparator ICMP trips, restarting the one-shot timer and initiating the next cycle. Inductor current is determined by sensing the voltage between the SENSE+ and SENSE- pins using the bottom MOSFET on-resistance . The voltage on the ITH pin sets the comparator threshold corresponding to inductor valley current. The error amplifier EA adjusts this ITH voltage by comparing 2/3 of the feedback signal VFB from the output voltage with a reference equal to 1/3 of the VREF voltage. If the load current increases, it causes a drop in the feedback voltage relative to the reference. The ITH voltage then rises until the average inductor current again matches the load current. As a result in normal DDR operation VOUT is equal to 1/2 of the VREF voltage. The operating frequency is determined implicitly by the top MOSFET on-time and the duty cycle required to maintain regulation. The one-shot timer generates an ontime that is proportional to the ideal duty cycle, thus holding frequency approximately constant with changes in VIN. The nominal frequency can be adjusted with an external resistor RON. Overvoltage and undervoltage comparators OV and UV pull the PGOOD output low if the output feedback voltage exits a 10% window around the regulation point.
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Furthermore, in an overvoltage condition, M1 is turned off and M2 is turned on and held on until the overvoltage condition clears. Pulling the RUN/SS pin low forces the controller into its shutdown state, turning off both M1 and M2. Releasing the pin allows an internal 1.2A current source to charge up an external soft-start capacitor CSS. When this voltage reaches 1.5V, the controller turns on and begins switching, but with the ITH voltage clamped at approximately 0.6V below the RUN/SS voltage. As CSS continues to charge, the soft-start current limit is removed. INTVCC/EXTVCC Power Power for the top and bottom MOSFET drivers and most of the internal controller circuitry is derived from the INTVCC pin. The top MOSFET driver is powered from a floating bootstrap capacitor CB. This capacitor is recharged from INTVCC through an external Schottky diode DB when the top MOSFET is turned off. When the EXTVCC pin is grounded, an internal 5V low dropout regulator supplies the INTVCC power from VCC. If EXTVCC rises above 4.7V, the internal regulator is turned off, and an internal switch connects EXTVCC to INTVCC. This allows a high efficiency source connected to EXTVCC, such as an external 5V supply or a secondary output from the converter, to provide the INTVCC power. Voltages up to 7V can be applied to EXTVCC for additional gate drive. If the VCC voltage is low and INTVCC drops below 3.4V, undervoltage lockout circuitry prevents the power switches from turning on.
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LTC3717-1
APPLICATIO S I FOR ATIO
A typical LTC3717-1 application circuit is shown in Figure 1. External component selection is primarily determined by the maximum load current and begins with the selection of the sense resistance and power MOSFET switches. The LTC3717-1 uses the on-resistance of the synchronous power MOSFET for determining the inductor current. The desired amount of ripple current and operating frequency largely determines the inductor value. Finally, CIN is selected for its ability to handle the large RMS current into the converter and COUT is chosen with low enough ESR to meet the output voltage ripple and transient specification. Maximum Sense Voltage and VRNG Pin Inductor current is determined by measuring the voltage across a sense resistance that appears between the SENSE + and SENSE - pins. The maximum sense voltage is set by the voltage applied to the VRNG pin and is equal to approximately (0.13)VRNG for sourcing current and (0.17)VRNG for sinking current. The current mode control loop will not allow the inductor current valleys to exceed (0.13)VRNG/RSENSE for sourcing current and (0.17)VRNG for sinking current. In practice, one should allow some margin for variations in the LTC3717-1 and external component values and a good guide for selecting the sense resistance is:
RSENSE = VRNG 10 * IOUT (MAX)
when VRNG = 0.5 - 2V. An external resistive divider from INTVCC can be used to set the voltage of the VRNG pin between 0.5V and 2V resulting in nominal sense voltages of 50mV to 200mV. Additionally, the VRNG pin can be tied to SGND or INTVCC in which case the nominal sense voltage defaults to 70mV or 140mV, respectively. The maximum allowed sense voltage is about 1.3 times this nominal value for positive output current and 1.7 times the nominal value for negative output current. Connecting the SENSE + and SENSE - Pins The LTC3717-1 can be used with or without a sense resistor. When using a sense resistor, it is placed between
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the source of the bottom MOSFET M2 and ground. Connect the SENSE + and SENSE - pins as a Kelvin connection to the sense resistor with SENSE + at the source of the bottom MOSFET and the SENSE - pin to PGND. Using a sense resistor provides a well defined current limit, but adds cost and reduces efficiency. Alternatively, one can eliminate the sense resistor and use the bottom MOSFET as the current sense element by simply connecting the SENSE + pin to the drain and the SENSE - pin to the source of the bottom MOSFET. This improves efficiency, but one must carefully choose the MOSFET on-resistance as discussed in a later section. Power MOSFET Selection The LTC3717-1 requires two external N-channel power MOSFETs, one for the top (main) switch and one for the bottom (synchronous) switch. Important parameters for the power MOSFETs are the breakdown voltage V(BR)DSS, threshold voltage V(GS)TH, on-resistance RDS(ON), reverse transfer capacitance CRSS and maximum current IDS(MAX). The gate drive voltage is set by the 5V INTVCC supply. Consequently, logic-level threshold MOSFETs must be used in LTC3717-1 applications. When the bottom MOSFET is used as the current sense element, particular attention must be paid to its on-resistance. MOSFET on-resistance is typically specified with a maximum value RDS(ON)(MAX) at 25C. In this case, additional margin is required to accommodate the rise in MOSFET on-resistance with temperature:
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RDS(ON)(MAX) =
RSENSE T
The T term is a normalization factor (unity at 25C) accounting for the significant variation in on-resistance with temperature, typically about 0.4%/C as shown in Figure 2. For a maximum junction temperature of 100C, using a value T = 1.3 is reasonable. The power dissipated by the top and bottom MOSFETs strongly depends upon their respective duty cycles and the load current. During normal operation, the duty cycles for the MOSFETs are:
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LTC3717-1
APPLICATIO S I FOR ATIO
2.0
T NORMALIZED ON-RESISTANCE
1.5
1.0
0.5
0 - 50
50 100 0 JUNCTION TEMPERATURE (C)
150
37171 F02
Figure 2. RDS(ON) vs. Temperature
D TOP = DBOT
VOUT VIN V -V = IN OUT VIN
The resulting power dissipation in the MOSFETs at maximum output current are: PTOP = DTOP IOUT(MAX)2 T(TOP) RDS(ON)(MAX) + k VIN2 IOUT(MAX) CRSS f PBOT = DBOT IOUT(MAX)2 T(BOT) RDS(ON)(MAX) Both MOSFETs have I2R losses and the top MOSFET includes an additional term for transition losses, which are largest at high input voltages. The constant k = 1.7A-1 can be used to estimate the amount of transition loss. The bottom MOSFET losses are greatest when the bottom duty cycle is near 100%, during a short-circuit or at high input voltage. Operating Frequency The choice of operating frequency is a tradeoff between efficiency and component size. Low frequency operation improves efficiency by reducing MOSFET switching losses but requires larger inductance and/or capacitance in order to maintain low output ripple voltage. The operating frequency of LTC3717-1 applications is determined implicitly by the one-shot timer that controls the on-time tON of the top MOSFET switch. The on-time is
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set by the current into the ION pin and the voltage at the VON pin according to:
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tON =
VVON (10pF ) IION
Tying a resistor RON from VIN to the ION pin yields an ontime inversely proportional to VIN. For a step-down converter, this results in approximately constant frequency operation as the input supply varies: f= VOUT [Hz] VVONRON (10pF )
To hold frequency constant during output voltage changes, tie the VON pin to VOUT. The VON pin has internal clamps that limit its input to the one-shot timer. If the pin is tied below 0.7V, the input to the one-shot is clamped at 0.7V. Similarly, if the pin is tied above 2.4V, the input is clamped at 2.4V. Because the voltage at the ION pin is about 0.7V, the current into this pin is not exactly inversely proportional to VIN, especially in applications with lower input voltages. To account for the 0.7V drop on the ION pin, the following equation can be used to calculate frequency:
f=
(VIN - 0.7V) * VOUT
VVON * VIN * RON (10pF )
To correct for this error, an additional resistor RON2 connected from the ION pin to the 5V INTVCC supply will further stabilize the frequency. RON2 = 5V RON 0.7V
Changes in the load current magnitude will also cause frequency shift. Parasitic resistance in the MOSFET switches and inductor reduce the effective voltage across the inductance, resulting in increased duty cycle as the load current increases. By lengthening the on-time slightly as current increases, constant frequency operation can be maintained. This is accomplished with a resistive divider from the ITH pin to the VON pin and VOUT. The values required will depend on the parasitic resistances in the specific application. A good starting point is to feed about
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LTC3717-1
APPLICATIO S I FOR ATIO
RVON1 30k VOUT RVON2 100k RC CVON 0.01F
VON LTC3717-1 ITH CC
(3a)
Figure 3. Adjusting Frequency Shift with Load Current Changes
25% of the voltage change at the ITH pin to the VON pin as shown in Figure 3a. Place capacitance on the VON pin to filter out the ITH variations at the switching frequency. The resistor load on ITH reduces the DC gain of the error amp and degrades load regulation, which can be avoided by using the PNP emitter follower of Figure 3b. Inductor L1 Selection Given the desired input and output voltages, the inductor value and operating frequency determine the ripple current:
V V IL = OUT 1 - OUT VIN fL
Lower ripple current reduces cores losses in the inductor, ESR losses in the output capacitors and output voltage ripple. Highest efficiency operation is obtained at low frequency with small ripple current. However, achieving this requires a large inductor. There is a tradeoff between component size, efficiency and operating frequency. A reasonable starting point is to choose a ripple current that is about 40% of IOUT(MAX). The largest ripple current occurs at the highest VIN. To guarantee that ripple current does not exceed a specified maximum, the inductance should be chosen according to:
VOUT V L= 1 - OUT f IL(MAX) VIN(MAX)
Once the value for L is known, the type of inductor must be selected. High efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite, molypermalloy
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RVON1 3k VOUT 10k INTVCC Q1 2N5087 RVON2 10k CVON 0.01F RC ITH CC
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VON LTC3717-1
(3b)
or Kool M(R) cores. A variety of inductors designed for high current, low voltage applications are available from manufacturers such as Sumida, Panasonic, Coiltronics, Coilcraft and Toko. Schottky Diode D1, D2 Selection The Schottky diodes, D1 and D2, shown in Figure 1 conduct during the dead time between the conduction of the power MOSFET switches. It is intended to prevent the body diodes of the top and bottom MOSFETs from turning on and storing charge during the dead time, which can cause a modest (about 1%) efficiency loss. The diodes can be rated for about one half to one fifth of the full load current since they are on for only a fraction of the duty cycle. In order for the diode to be effective, the inductance between it and the bottom MOSFET must be as small as possible, mandating that these components be placed adjacently. The diodes can be omitted if the efficiency loss is tolerable. CIN and COUT Selection The input capacitance CIN is required to filter the square wave current at the drain of the top MOSFET. Use a low ESR capacitor sized to handle the maximum RMS current. IRMS IOUT (MAX) VOUT VIN VIN -1 VOUT
This formula has a maximum at VIN = 2VOUT, where IRMS = IOUT(MAX) / 2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that ripple current ratings from capacitor manufacturers are often
Kool M is a registered trademark of Magnetics, Inc.
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APPLICATIO S I FOR ATIO
based on only 2000 hours of life which makes it advisable to derate the capacitor. The selection of COUT is primarily determined by the ESR required to minimize voltage ripple and load step transients. The output ripple VOUT is approximately bounded by:
1 VOUT IL ESR + 8fC OUT
Since IL increases with input voltage, the output ripple is highest at maximum input voltage. Typically, once the ESR requirement is satisfied, the capacitance is adequate for filtering and has the necessary RMS current rating. Multiple capacitors placed in parallel may be needed to meet the ESR and RMS current handling requirements. Dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. Special polymer capacitors offer very low ESR but have lower capacitance density than other types. Tantalum capacitors have the highest capacitance density but it is important to only use types that have been surge tested for use in switching power supplies. Aluminum electrolytic capacitors have significantly higher ESR, but can be used in cost-sensitive applications providing that consideration is given to ripple current ratings and long term reliability. Ceramic capacitors have excellent low ESR characteristics but can have a high voltage coefficient and audible piezoelectric effects. The high Q of ceramic capacitors with trace inductance can also lead to significant ringing. When used as input capacitors, care must be taken to ensure that ringing from inrush currents and switching does not pose an overvoltage hazard to the power switches and controller. To dampen input voltage transients, add a small 5F to 50F aluminum electrolytic capacitor with an ESR in the range of 0.5 to 2. High performance through-hole capacitors may also be used, but an additional ceramic capacitor in parallel is recommended to reduce the effect of their lead inductance. Top MOSFET Driver Supply (CB, DB) An external bootstrap capacitor CB connected to the BOOST pin supplies the gate drive voltage for the topside MOSFET. This capacitor is charged through diode DB from INTVCC when the switch node is low. When the top MOSFET turns
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on, the switch node rises to VIN and the BOOST pin rises to approximately VIN + INTVCC. The boost capacitor needs to store about 100 times the gate charge required by the top MOSFET. In most applications a 0.1F to 0.47F X5R or X7R dielectric capacitor is adequate. Fault Condition: Current Limit The maximum inductor current is inherently limited in a current mode controller by the maximum sense voltage. In the LTC3717-1, the maximum sense voltage is controlled by the voltage on the VRNG pin. With valley current control, the maximum sense voltage and the sense resistance determine the maximum allowed inductor valley current. The corresponding output current limit is: ILIMITPOSITIVE = ILIMITNEGATIVE = VSNS(MAX) 1 + IL RDS(ON)T 2 VSNS(MAX) 1 - IL RDS(ON)T 2 The current limit value should be checked to ensure that ILIMIT(MIN) > IOUT(MAX). The minimum value of current limit generally occurs with the largest VIN at the highest ambient temperature, conditions that cause the largest power loss in the converter. Note that it is important to check for self-consistency between the assumed MOSFET junction temperature and the resulting value of ILIMIT which heats the MOSFET switches. Caution should be used when setting the current limit based upon the RDS(ON) of the MOSFETs. The maximum current limit is determined by the minimum MOSFET onresistance. Data sheets typically specify nominal and maximum values for RDS(ON), but not a minimum. A reasonable assumption is that the minimum RDS(ON) lies the same amount below the typical value as the maximum lies above it. Consult the MOSFET manufacturer for further guidelines. Minimum Off-time and Dropout Operation The minimum off-time tOFF(MIN) is the smallest amount of time that the LTC3717-1 is capable of turning on the bottom MOSFET, tripping the current comparator and turning the MOSFET back off. This time is generally about
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LTC3717-1
APPLICATIO S I FOR ATIO
250ns. The minimum off-time limit imposes a maximum duty cycle of tON/(tON + tOFF(MIN)). If the maximum duty cycle is reached, due to a dropping input voltage for example, then the output will drop out of regulation. The minimum input voltage to avoid dropout is: VIN(MIN) = VOUT tON + tOFF(MIN) tON
Output Voltage Programming When VFB is connected to VOUT, the output voltage is regulated to one half of the voltage at the VREF pin. A resistor connected between VFB and VOUT can be used to further adjust the output voltage according to the following equation: Soft-Start and Latchoff with the RUN/SS Pin The RUN/SS pin provides a means to shut down the LTC3717-1 as well as a timer for soft-start and overcurrent latchoff. Pulling the RUN/SS pin below 0.8V puts the LTC3717-1 into a low quiescent current shutdown (IQ < 30A). Releasing the pin allows an internal 1.2A current source to charge up the external timing capacitor CSS. If RUN/SS has been pulled all the way to ground, there is a delay before starting of about:
tDELAY = 1.5V C SS = 1.3s/F C SS 1.2A
60k + RFB VOUT = VREF 120k
If VREF exceeds 3V, resistors should be placed in series with the VREF pin and the VFB pin to avoid exceeding the input common mode range of the internal error amplifier. To maintain the VOUT = VREF/2 relationship, the resistor in series with the VREF pin should be made twice as large as the resistor in series with the VFB pin.
RFB 249k VOUT RFB 499k VREF VFB LTC3717-1 VREF
37171 F04
Figure 4
External Gate Drive Buffers The LTC3717-1 drivers are adequate for driving up to about 30nC into MOSFET switches with RMS currents of 50mA. Applications with larger MOSFET switches or operating at frequencies requiring greater RMS currents will benefit from using external gate drive buffers such as the LTC1693. Alternately, the external buffer circuit shown in Figure 5 can be used. Note that the bipolar devices reduce the signal swing at the MOSFET gate.
3.3V OR 5V D1
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BOOST Q1 FMMT619 10 TG Q2 FMMT720 SW GATE OF M1 10 BG Q4 FMMT720 PGND
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DRVCC Q3 FMMT619 GATE OF M2
Figure 5. Optional External Gate Driver
(
)
When the voltage on RUN/SS reaches 1.5V, the LTC37171 begins operating with a clamp on ITH of approximately 0.9V. As the RUN/SS voltage rises to 3V, the clamp on ITH is raised until its full 2.4V range is available. This takes an additional 1.3s/F, during which the load current is folded back. During start-up, the maximum load current is reduced until either the RUN/SS pin rises to 3V or the output reaches 75% of its final value. The pin can be driven from logic as shown in Figure 6. Diode D1 reduces the start delay while allowing CSS to charge up slowly for the softstart function.
INTVCC RSS* RUN/SS RSS* D2* RUN/SS
VIN
CSS
CSS
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*OPTIONAL TO OVERRIDE OVERCURRENT LATCHOFF
(6a)
(6b)
Figure 6. RUN/SS Pin Interfacing with Latchoff Defeated
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After the controller has been started and given adequate time to charge up the output capacitor, CSS is used as a short-circuit timer. After the RUN/SS pin charges above 4V, if the output voltage falls below 75% of its regulated value, then a short-circuit fault is assumed. A 1.8A current then begins discharging CSS. If the fault condition persists until the RUN/SS pin drops to 3.5V, then the controller turns off both power MOSFETs, shutting down the converter permanently. The RUN/SS pin must be actively pulled down to ground in order to restart operation. The overcurrent protection timer requires that the softstart timing capacitor CSS be made large enough to guarantee that the output is in regulation by the time CSS has reached the 4V threshold. In general, this will depend upon the size of the output capacitance, output voltage and load current characteristic. A minimum soft-start capacitor can be estimated from: CSS > COUT VOUT RSENSE (10 - 4 [F/V s]) Generally 0.1F is more than sufficient. Overcurrent latchoff operation is not always needed or desired. Load current is already limited during a shortcircuit by the current foldback circuitry and latchoff operation can prove annoying during troubleshooting. The feature can be overridden by adding a pull-up current greater than 5A to the RUN/SS pin. The additional current prevents the discharge of CSS during a fault and also shortens the soft-start period. Using a resistor to V IN as shown in Figure 6a is simple, but slightly increases shutdown current. Connecting a resistor to INTV CC as shown in Figure 6b eliminates the additional shutdown current, but requires a diode to isolate C SS. Any pull-up network must be able to pull RUN/SS above the 4.2V maximum threshold of the latchoff circuit and overcome the 4A maximum discharge current. INTVCC Regulator An internal P-channel low dropout regulator produces the 5V supply that powers the drivers and internal circuitry within the LTC3717-1. The INTVCC pin can supply up to 50mA RMS and must be bypassed to ground with a minimum of 4.7F tantalum or other low ESR capacitor. Good bypassing is necessary to supply the high transient
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currents required by the MOSFET gate drivers. Applications using large MOSFETs with a high input voltage and high frequency of operation may cause the LTC3717-1 to exceed its maximum junction temperature rating or RMS current rating. Most of the supply current drives the MOSFET gates unless an external EXTVCC source is used. In continuous mode operation, this current is IGATECHG = f(Qg(TOP) + Qg(BOT)). The junction temperature can be estimated from the equations given in Note 2 of the Electrical Characteristics. For example, the LTC3717EUH-1 is limited to less than 14mA from a 30V supply: TJ = 70C + (14mA)(30V)(34C/W) = 84.3C For larger currents, consider using an external supply with the EXTVCC pin. EXTVCC Connection The EXTVCC pin can be used to provide MOSFET gate drive and control power from the output or another external source during normal operation. Whenever the EXTVCC pin is above 4.7V the internal 5V regulator is shut off and an internal 50mA P-channel switch connects the EXTVCC pin to INTVCC. INTVCC power is supplied from EXTVCC until this pin drops below 4.5V. Do not apply more than 7V to the EXTVCC pin and ensure that EXTVCC VCC. The following list summarizes the possible connections for EXTVCC: 1. EXTVCC grounded. INTVCC is always powered from the internal 5V regulator. 2. EXTVCC connected to an external supply. A high efficiency supply compatible with the MOSFET gate drive requirements (typically 5V) can improve overall efficiency. 3. EXTVCC connected to an output derived boost network. The low voltage output can be boosted using a charge pump or flyback winding to greater than 4.7V. The system will start-up using the internal linear regulator until the boosted output supply is available. Efficiency Considerations The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine
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LTC3717-1
APPLICATIO S I FOR ATIO
what is limiting the efficiency and which change would produce the most improvement. Although all dissipative elements in the circuit produce losses, four main sources account for most of the losses in LTC3717-1 circuits: 1. DC I2R losses. These arise from the resistances of the MOSFETs, inductor and PC board traces and cause the efficiency to drop at high output currents. In continuous mode the average output current flows through L, but is chopped between the top and bottom MOSFETs. If the two MOSFETs have approximately the same RDS(ON), then the resistance of one MOSFET can simply be summed with the resistances of L and the board traces to obtain the DC I2R loss. For example, if RDS(ON) = 0.01 and RL = 0.005, the loss will range from 1% up to 10% as the output current varies from 1A to 10A for a 1.5V output. 2. Transition loss. This loss arises from the brief amount of time the top MOSFET spends in the saturated region during switch node transitions. It depends upon the input voltage, load current, driver strength and MOSFET capacitance, among other factors. The loss is significant at input voltages above 20V and can be estimated from: Transition Loss (1.7A-1) VIN2 IOUT CRSS f 3. INTVCC current. This is the sum of the MOSFET driver and control currents. 4. CIN loss. The input capacitor has the difficult job of filtering the large RMS input current to the regulator. It must have a very low ESR to minimize the AC I2R loss and sufficient capacitance to prevent the RMS current from causing additional upstream losses in fuses or batteries. Other losses, including COUT ESR loss, Schottky diode D1 conduction loss during dead time and inductor core loss generally account for less than 2% additional loss. When making adjustments to improve efficiency, the input current is the best indicator of changes in efficiency. If you make a change and the input current decreases, then the efficiency has increased. If there is no change in input current, then there is no change in efficiency.
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Checking Transient Response The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, VOUT immediately shifts by an amount equal to ILOAD (ESR), where ESR is the effective series resistance of COUT. ILOAD also begins to charge or discharge COUT generating a feedback error signal used by the regulator to return VOUT to its steady-state value. During this recovery time, VOUT can be monitored for overshoot or ringing that would indicate a stability problem. The ITH pin external components shown in Figure 1 will provide adequate compensation for most applications. For a detailed explanation of switching control loop theory see Application Note 76. Design Example As a design example, take a supply with the following specifications: VIN = VREF = 2.5V, VEXTVCC = 5V, VOUT = 1.25V 5%, IOUT(MAX) = 10A, f = 250kHz. First, calculate the timing resistor with VON = VOUT:
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RON =
1.25V(2.5V - 0.7V) = 514k (0.7V)(250kHz)(10pF )2.5V
and choose the inductor for about 40% ripple current at the maximum VIN:
L=
1.25V 1.25V 1- = 0.63H (250kHz)(0.4)(10A) 2.5V
Selecting a standard value of 0.68H results in a maximum ripple current of:
IL = 1.25V 1.25V 1- = 3.7A (250kHz)(0.68H) 2.5V
Next, choose the synchronous MOSFET switch. Choosing a Si4874 (RDS(ON) = 0.0083 (NOM) 0.010 (MAX), JA = 40C/W) yields a nominal sense voltage of: VSNS(NOM) = (10A)(1.3)(0.0083) = 108mV
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APPLICATIO S I FOR ATIO
Tying VRNG to 1.1V will set the current sense voltage range for a nominal value of 110mV with current limit occurring at 143mV. To check if the current limit is acceptable, assume a junction temperature of about 40C above a 70C ambient with 110C = 1.4:
ILIMIT 143mV 1 + (3.7A) = 12.1A (1.4)(0.010) 2
and double check the assumed TJ in the MOSFET: PBOT 2.5V - 1.25V = (12.1A)2 (1.4)(0.010) = 1.02 W 2.5V
TJ = 70C + (1.02W)(40C/W) = 111C Because the top MOSFET is on roughly the same amount of time as the bottom MOSFET, the same Si4874 can be used as the synchronous MOSFET. The junction temperatures will be significantly less at nominal current, but this analysis shows that careful attention to heat sinking will be necessary in this circuit. CIN is chosen for an RMS current rating of about 5A at 85C. The output capacitors are chosen for a low ESR of
CSS 0.1F RUN/SS R3 11k R4 39k RPG 100k PGOOD CC1 470pF TG LTC3717-1 SW VRNG SENSE + ITH CC2 100pF CON 0.01F SGND VON ION VFB VREF RON 511k (OPT) 0.1F INTVCC DRVCC VCC EXTVCC 10 PGND SENSE - BG CVCC 4.7F RF 1 BOOST CB 0.22F DB CMDSH-3
RC 20k
CIN, COUT1-2: CORNELL DUBILIER ESRE181E04B L1: SUMIDA CEP125-0R68MC-H
Figure 7. Design Example: 1.25V/10A at 250kHz
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0.013 to minimize output voltage changes due to inductor ripple current and load steps. For current sinking applications where current flows back to the input through the top transistor, output capacitors with a similar amount of bulk C and ESR should be placed on the input as well. (This is typically the case, since VIN is derived from another DC/DC converter.) The ripple voltage will be only: VOUT(RIPPLE) = IL(MAX) (ESR) = (4A) (0.013) = 52mV However, a 0A to 10A load step will cause an output change of up to: VOUT(STEP) = ILOAD (ESR) = (10A) (0.013) = 130mV An optional 22F ceramic output capacitor is included to minimize the effect of ESL in the output ripple. The complete circuit is shown in Figure 7. PC Board Layout Checklist When laying out a PC board follow one of the two suggested approaches. The simple PC board layout requires a dedicated ground plane layer. Also, for higher currents, it is recommended to use a multilayer board to help with heat sinking power components.
M1 Si4874 D2 B320A CIN 22F 6.3V X7R
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L1 0.68H M2 Si4874 D1 B320A
+
COUT1-2 270F 2V x2
VIN = 2.5V CIN 180F 4V x2 VOUT 1.25V 10A COUT3 22F 6.3V X7R
VEXT 5V CF 0.1F
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LTC3717-1
APPLICATIO S I FOR ATIO
* The ground plane layer should not have any traces and it should be as close as possible to the layer with power MOSFETs. * Place CIN, COUT, MOSFETs, D1 and inductor all in one compact area. It may help to have some components on the bottom side of the board. * Place LTC3717-1 chip with Pins 15 to 28 facing the power components. Keep the components connected to Pins 1 to 10 close to LTC3717-1 (noise sensitive components). * Use an immediate via to connect the components to ground plane including SGND and PGND of LTC3717-1. Use several bigger vias for power components. * Use compact plane for switch node (SW) to improve cooling of the MOSFETs and to keep EMI down. * Use planes for VIN and VOUT to maintain good voltage filtering and to keep power losses low. * Flood all unused areas on all layers with copper. Flooding with copper will reduce the temperature rise of power component. You can connect the copper areas to any DC net (VIN, VOUT, GND or to any other DC rail in your system).
CSS RUN/SS PGOOD BOOST TG DB CB
LTC3717-1 VRNG SW CC1 RC ITH CC2 SGND CION CFB VFB VREF RON VON ION INTVCC DRVCC VCC EXTVCC SENSE + PGND SENSE - BG
+
BOLD LINES INDICATE HIGH CURRENT PATHS
Figure 8. LTC3717-1 Layout Diagram
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When laying out a printed circuit board, without a ground plane, use the following checklist to ensure proper operation of the controller. These items are also illustrated in Figure 8. * Segregate the signal and power grounds. All small signal components should return to the SGND pin at one point which is then tied to the PGND pin close to the source of M2. * Place M2 as close to the controller as possible, keeping the PGND, BG and SW traces short. * Connect the input capacitor(s) CIN close to the power MOSFETs. This capacitor carries the MOSFET AC current. * Keep the high dV/dT SW, BOOST and TG nodes away from sensitive small-signal nodes. * Connect the INTVCC and DRVCC decoupling capacitor CVCC closely to the INTVCC, DRVCC and PGND pins. * Connect the top driver boost capacitor CB closely to the BOOST and SW pins. * Connect the VCC pin decoupling capacitor CF closely to the VCC and PGND pins.
L M1
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VIN CIN
M2 CVCC
D2 D1
- -
CF RF COUT VOUT
+
37171 F08
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LTC3717-1
TYPICAL APPLICATIO S
1.5V/10A at 300kHz from 5V to 28V Input
CSS 0.1F RUN/SS RR1 11k RR2 39k RPG 100k PGOOD LTC3717-1 CC1 680pF RC 20k VRNG ITH CC2 100pF CON 0.01F SGND VON ION VFB VREF 3V 10F 6.3V X7R RON 510k VREF INTVCC DRVCC VCC EXTVCC SW SENSE + PGND SENSE - BG CVCC 4.7F M2 IRF7822 L1 1.2H D1 B320A TG BOOST CB 0.22F M1 IRF7811W B320A DB CMDSH-3 VIN CIN 5V TO 28V 10F 35V VOUT x3 1.5V 10A COUT 270F 2V x2
COUT: CORNELL DUBILIER ESRE271M02B
CSS 0.1F RUN/SS RPG 100k PGOOD TG LTC3717-1 VRNG SW SENSE + ITH CC2 100pF CON 0.01F SGND VON ION VFB VREF INTVCC DRVCC VCC EXTVCC R1 2M C2 2200pF PGND SENSE - BG BOOST
CC1 470pF
RC 20k
RON 510k R2 1M
CIN: TAIYO YUDEN TMK432BJ106MM COUT1: SANYO, OS-CON 16SP270 COUT2: TAIYO YUDEN JMK316BJ106ML L1: TOKO 919AS-1R8N
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High Voltage Half (VIN) Power Supply
DB CMDSH-3 CB 0.22F CIN 10F 25V x2 VIN 5V TO 25V
M1 FDS6680S L1 1.8H M2 FDS6680S
+
VOUT VIN/2 6A COUT2 10F 15V
COUT1 270F 16V
CVCC 4.7F RF 1 CF 0.1F
37171 TA02
LTC3717-1
PACKAGE DESCRIPTIO
5.35 0.05 4.20 0.05 3.45 0.05 (4 SIDES)
RECOMMENDED SOLDER PAD LAYOUT 5.00 0.10 (4 SIDES) 0.75 0.05 0.00 - 0.05
PIN 1 TOP MARK
NOTE: 1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE M0-220 VARIATION WHHD-(X) (TO BE APPROVED) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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UH Package 32-Lead Plastic QFN (5mm x 5mm)
(Reference LTC DWG # 05-08-1693)
0.57 0.05 PACKAGE OUTLINE 0.23 0.05 0.50 BSC BOTTOM VIEW--EXPOSED PAD R = 0.115 TYP 31 32 0.40 0.10 1 2 3.45 0.10 (4-SIDES)
(UH) QFN 0102
0.200 REF
0.23 0.05 0.50 BSC
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LTC3717-1
TYPICAL APPLICATIO
CSS 0.1F
RPG 100k PGOOD LTC3717-1 CC1 470pF VRNG RC 33k CC2 100pF CON, 0.01F ITH SGND VON ION VFB VREF RON 92k INTVCC DRVCC VCC EXTVCC SW SENSE + PGND SENSE - BG TG
CIN, COUT: CORNELL DUBILIER ESRD121M04B L1: TOKO A921CY-0R7M
RELATED PARTS
PART NUMBER LTC1625/LTC1775 LTC1628-PG LTC1628-SYNC LTC1709-7 LTC1709-8 LTC1735 LTC1736 LTC1772 LTC1773 LTC1778/LTC3778 LTC1874 LTC1876 LTC3413 LTC3717 DESCRIPTION No RSENSE Current Mode Synchronous Step-Down Controller Dual, 2-Phase Synchronous Step-Down Controller Dual, 2-Phase Synchronous Step-Down Controller High Efficiency, 2-Phase Synchronous Step-Down Controller with 5-Bit VID High Efficiency, 2-Phase Synchronous Step-Down Controller High Efficiency, Synchronous Step-Down Controller High Efficiency, Synchronous Step-Down Controller with 5-Bit VID SOT-23 Step-Down Controller Synchronous Step-Down Controller Wide Operating Range, No RSENSE Step-Down Synchronous Controllers Dual, Step-Down Controller 2-Phase, Dual Synchronous Step-Down Controller with Step-Up Regulator Monolithic DDR Memory Termination Regulator Wide Operating Range, No RSENSE Step-Down Synchronous Controllers for DDR Memory Termination
TM
Burst Mode is a registered trademark of Linear Technology Corporation.
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20 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 q FAX: (408) 434-0507
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Typical Application 1.25V/3A at 1.4MHz
DB CMDSH-3 RUN/SS BOOST CB 0.22F M1 1/2 Si9802 L1 0.7H
+
CIN 120F 4V
VIN 2.5V
+
M2 1/2 Si9802
VOUT 1.25V 3A
COUT 120F 4V
CVCC 4.7F
5V
1F
3717 TA03
COMMENTS 97% Efficiency; No Sense Resistor; 99% Duty Cycle Power Good Output; Minimum Input/Output Capacitors; 3.5V VIN 36V Synchronizable 150kHz to 300kHz Up to 42A Output; 0.925V VOUT 2V Up to 42A Output; VRM 8.4; 1.3V VOUT 3.5V Burst ModeTM Operation; 16-Pin Narrow SSOP; 3.5V VIN 36V Mobile VID; 0.925V VOUT 2V; 3.5V VIN 36V Current Mode; 550kHz; Very Small Solution Size Up to 95% Efficiency, 550kHz, 2.65V VIN 8.5V, 0.8V VOUT VIN, Synchronizable to 750kHz 4V VIN 36V, True Current Mode Control, 2% to 90% Duty Cycle Current Mode; 550kHz; Small 16-Pin SSOP, VIN < 9.8V 2.6V VIN 36V, Power Good Output, 300kHz Operation 90% Efficiency, 3A Output, 2MHz Operation 4V VIN 36V, True Current Mode Control, 2% to 90% Duty Cycle, 16-Pin SSOP, No RSENSE
LT/TP 0603 1K * PRINTED IN USA
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2003

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